"VLSI Implementation of High Resolution High Speed Low Latency Pipeline Floating point Adder/Subtractor for FFT Applications" by Rozita Teymourzadeh, et al.

VLSI Implementation of High Resolution High Speed Low Latency Pipeline Floating point Adder/Subtractor for FFT Applications

Rozita Teymourzadeh, Faculty of Engineering, Technology and Built Environment UCSI University
Burhan Yeop Majlis, IMEN
Mok VH, UCSI
Masuri Othman, Mosti

Article comments

IMEN

Abstract

This paper presents on-chip implementation of high speed low latency floating point adder /subtractor with high accuracy performance for FFT in OFDM transceiver. However due to high performance and high resolution, the floating point adder is matched with power network applications as well. The design was implemented for 32-bit pipelined adder/subtractor which satisfied IEEE-754 Standard for floating -point Arithmetic. The design is focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and investigated. Consequently, synthesis report indicating the latency of 4 clock cycles due to each stage operate within just one clock cycle. The unique structure of designed adder well thought out. The synthesis software provides results representing the estimated area and delay for design when it is pipelined to various depths.

Suggested Citation

Rozita Teymourzadeh, Burhan Yeop Majlis, Mok VH, and Masuri Othman. "VLSI Implementation of High Resolution High Speed Low Latency Pipeline Floating point Adder/Subtractor for FFT Applications"International Conference on NanoTech (2009): 327-331.
Available at: http://works.bepress.com/rozita_teymourzadeh/8

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"VLSI Implementation of High Resolution H" by Rozita Teymourzadeh, et al.

Publications | Rozita Teymourzadeh | Official Website

Year: 2012

• Aravind C, Grace I, Teymourzadeh R, Rajparthiban R, Rajprasad R, Wong Y. Universal computer aided design for electrical machines. In: IEEE 8th International colloquium on signal Processing Applications conference (CSPA 2012); Malaysia: IEEE; 2012. 99-104. [More] [Full text] [Bibtex]

Year: 2011

• Algnabi Y. S, Teymourzadeh R, Othman M, Islam M. S. FPGA Implementation of Pipeline Digit-Slicing Multiplier-Less Radix 22 DIF SDF Butterfly for Fast Fourier Transform Structure. IEEE; 2011. [More] [Full text] [Bibtex]
• Grace I, RozitaTeymourzadeh, Bright S, Aravind C. Optimised toolbox for the design of rotary reluctance motors. In: 2011 IEEE Conference on Sustainable Utilization and Development in Engineering and Technology; Malaysia: IEEE; 2011. 1-6.[More] [Full text] [Bibtex]

Year: 2010

• Algnabi Y. S, Teymourzadeh R, Othman M, Islam M. S, Hong M. V. On-Chip Implementation of Pipeline Digit-Slicing Multiplier-Less Butterfly for Fast Fourier Transform Architecture. American Journal of Engineering and Applied Sciences2010;3(4):757-764. [More] [Full text] [Bibtex]
• Teymourzadeh R, Othman M, Islam M. S, Algnabi Y. S, Hong J. M. VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers_1. American Journal of Engineering and Applied Sciences 2010;3(4):663-669. [More] [Full text] [Bibtex]
• RozitaTeymourzadeh, Algnabi Y. S, Mahdavi N, Othman M. B. On-Chip Implementation of High Resolution High Speed Floating Point Adder/Subtractor with Reducing Mean Latency for OFDM. American Journal of Engineering and Applied Sciences 2010;3(1):25-30. [More] [Full text] [Bibtex]
• Hoe C. K, Vaithlingam A. C, RozitaTeymourzadeh, Rajkumar R. Design of automatic soil humidity control using Maximum Power Point Tracking controller. In: IEEE Student Conference on Research and Development, SCOReD 2010; Malaysia: IEEE; 2010. 387-391. [More] [Full text] [Bibtex]
• Samir Y, RozitaTeymourzadeh. The effect of the digit slicing architecture on the FFT butterfly. In: IEEE International Conference on Information Science Signal Processing and their Application. ISSPA 2010; Malaysia: IEEE; 2010. 802-805.[More] [Full text] [Bibtex]

Year: 2009

• RozitaTeymourzadeh, Majlis B. Y, Mok V, Othman M. B. VLSI Implementation of High Resolution High Speed Low Latency Pipeline Floating point Adder/Subtractor for FFT Applications. IMEN; 2009. [More] [Full text] [Bibtex]

Year: 2007

• Mahdavi N, Teymourzadeh R, Othman M. On-Chip Implementation of High Speed and High resolution Pipeline Radix 2 FFT Algorithm. Ieee; 2007. [More] [Full text] [Bibtex]
• Mahdavi N, Teymourzadeh R, Othman M. B. VLSI implementation of high speed and high resolution FFT algorithm based on radix 2 for DSP application. In: IEEE Student Conference on Research and Development, SCOReD 2007; Malaysia: IEEE; 2007. 1-4. [More] [Full text] [Bibtex]

Year: 2006

• RozitaTeymourzadeh, Othman M. An Improved Recursive and Non-recursive Comb Filter for DSP Applications. The 6th Asian Control Conference. Institute Technology Bandung & IEEE Indonesia; 2006. [More] [Full text] [Bibtex]
• Teymourzadeh R, Othman M. An Overview of the Decimation process and its VLSI implementation. UKM; 2006. [More] [Full text] [Bibtex]
• RozitaTeymourzadeh, Othman M. B. An Enhancement of Decimation Process using Fast Cascaded Integrator Comb (CIC) Filter. In: IEEE International Conference on Semiconductor Electronics (ICSE); Malaysia: IEEE; 2006. 811-815.[More] [Full text] [Bibtex]
• RozitaTeymourzadeh, Othman M. VLSI Implementation of Cascaded Integrator Comb Filters for DSP Applications. University of Malaya; 2006. [More] [Full text] [Bibtex]

Year: 2005

• Teymourzadeh R, Othman M. On-Chip Implementation of Cascaded Integrated Comb filters (CIC) for DSP Application. Faculty of Engineering, National University of Malaysia; 2005. [More] [Full text] [Bibtex]

Publications | Rozita Teymourzadeh | Official Website